A vertical MOSFET (Metal oxide semiconductor field-effect transistor) is a widely known semiconductor device. In a proposed vertical MOSFET, a source electrode and a gate electrode formed via a gate insulation film are disposed on one surface of a semiconductor; a drain electrode is disposed on the other surface of the semiconductor; the semiconductor includes a base layer performing a function of one conductive type among N and P types, a first portion partially formed on a given surface of the base layer to perform a function of the other conductive type among N and P types, and a second portion partially formed on a surface of the first portion to perform a function of the one conductive type and having a surface connected to the source electrode; the given surface of the base layer, the surface of the first portion, and the surface of the second portion are exposed as constituent surfaces of one surface of the semiconductor; the first portion is located to be interposed between the given surface of the base layer and the surface of the second portion; and the drain electrode is disposed on the other surface of the base layer (see, e.g., Patent Document 1 (FIG. 3, etc.)).
FIG. 10 is a cross-sectional diagram of a cross section structure of a conventional MOSFET. As depicted in FIG. 10, for example, in the vertical MOSFET, a base layer of a semiconductor is a layer including an N-type SiC substrate 1 and an N-type SiC layer 2 formed on one surface of the N-type SiC substrate 1. Multiple P-type regions 3 are formed as the first portion in a surface layer of the N-type SiC layer 2 (a surface layer on the opposite side to the N-type SiC substrate 1 side). An N-type source region 4 and a P-type contact region 5 are formed as the second portion in the surface layer of the P-type region 3 (a surface layer on the opposite side to the N-type SiC substrate 1 side). A source electrode 8 is formed on the surfaces of the N-type source region 4 and the P-type contact region 5. A gate electrode 7 is formed via a gate insulation film 6 on one surface of the N-type SiC layer 2 (a surface on the opposite side to the N-type SiC substrate 1 side) and a surface of the P-type region 3 between the N-type SiC layer 2 and the N-type source region 4. A drain electrode 9 is formed on the other surface (back surface) of the N-type SiC substrate 1.
FIG. 11 is a cross-sectional diagram of a cross section structure of another conventional MOSFET. As depicted in FIG. 11, in another vertical MOSFET, a base layer of a semiconductor is used that has the N-type SiC layer 2 formed on one surface of the N-type SiC substrate 1, and multiple P-type regions 10 (the first portion) are formed in a surface layer of the N-type SiC layer 2 (a surface layer on a side opposite to the N-type SiC substrate 1 side). A P-type SiC layer 11 (the first portion) is formed on a surface of each of the P-type regions 10 and a surface of the N-type SiC layer 2 (a surface on the opposite side to the N-type SiC substrate 1 side). An N-type source region 4 and a P-type contact region 5 are formed as the second portion in a surface layer of the P-type SiC layer 11 (a surface layer on the opposite side to the N-type SiC substrate 1 side). The source electrode 8 is formed on the surfaces of the N-type source region 4 and the P-type contact region 5. On the other hand, an N-type region 12 is formed in the P-type SiC layer 11 on a region where the N-type SiC layer 2 exists without formation of the P-type region 10 such that the N-type SiC layer 2 appears. The gate electrode 7 is formed via the gate insulation film 6 on a surface of the N-type region 12 and a surface of the P-type SiC layer 11 between the N-type region 12 and the N-type source region 4. The drain electrode 9 is formed on the other surface (back surface) of the N-type SiC substrate 1.
In these vertical MOSFETs, when a positive voltage is applied to the drain electrode 9 relative to the source electrode 8, if a voltage less than a gate threshold value is applied to the gate electrode 7, PN-junction between the P-type region 3 and the N-type SiC layer 2 (see FIG. 10) or PN-junction between the P-type SiC layer 11 and the N-type region 12 (see FIG. 11) is inversely-biased and therefore, no current flows. On the other hand, if a voltage equal to or greater than the gate threshold value is applied to the gate electrode 7, the formation of an inversion layer on the surface of the P-type region 3 (see FIG. 10) or the surface of the P-type SiC layer 11 (see FIG. 11) immediately below the gate electrode 7 causes current to flow. Thus, the switching operation of the MOSFETs can be achieved by the voltage applied to the gate electrode 7.    Patent Document 1: Japanese Laid-open Patent Publication No. H10-107263